Abstract: Multi-core processors have become the mainstream of processors and have developed into mainstream processing platforms for various communications and media applications. The communication structure is one of the core technologies in a multi-core system, and the efficiency of inter-core communication is an important indicator that affects the performance of a multi-core processor. There are currently three main communication architectures: bus system structure, crossbar network and network on chip. The bus structure design is relatively convenient, the hardware consumption is less, and the cost is lower; the crossbar switch is a switching network structure suitable for building large-capacity systems; and the network-on-chip is a higher-level and larger-scale network-on-chip system that can currently solve multi-core The architecture problem is one of the most promising solutions for multi-core systems. While analyzing the basic principles, system structure and functions of the NoC structure, the article also provides the design and implementation of some units. Keywords: multi-core processor; inter-core communication; bus structure; crossbar switch; network on chip In the development of processors, it has become more and more difficult to increase the processor's main frequency. It is difficult to see traditional single processors with a chip's main frequency higher than 4 CHz on the market. Represented by Intel and AMD, the era of improving system performance by continuously increasing processor frequency is about to pass. There are three reasons for this: firstly, it is difficult to greatly improve the performance of the CPU only by increasing the main frequency, thereby slowing down consumers' enthusiasm for high-frequency CPUs; secondly, when the CPU main frequency reaches 2 GHz or more, the processor power consumption also reaches In the field of embedded products, the traditional single-core processor structure cannot meet the demand for geometrically increasing computing scale. In the single-core mode, the development of using local performance to improve overall performance is getting slower and slower, while the thread-level parallel technology based on multi-core provides the impetus for performance improvement. In order to achieve higher processing efficiency, a multi-core processor architecture emerged. . A multi-core processor is a chip containing two or more "execution cores". Multi-core processors face more challenges than single-core processors in the technical research of the architecture, such as inter-core communication, memory system, low power consumption, and software and hardware coordination. How to achieve mutual cooperation and communication between multi-core cores, to ensure that the processing speed is increased, and the performance of the chip processor is improved, which is the main content of the research on the communication structure between cores. In the multi-core communication method, in addition to continuing to use the bus structure in the single-core SoC, such as AMBA, CoreConnect, Wishbone, OCP, C*BUS, etc., there are mainly crossbar switches (NoC, Network on-Chip) ) And other structures. Among them, the NoC structure is a higher-level and larger-scale network system on a chip, which can solve the problem of multi-core architecture at present, and is one of the effective solutions for multi-core systems. 1 The problems solved by NoC and their advantages With the advancement of technology, product performance, area, power consumption, and time-to-market restrictions have made design and development requirements higher and higher. The problems caused by deep sub-micron design make it more difficult to ensure timing closure in the design. The emergence of NoC (Network on-Chip) has brought the continuous development of deep sub-micron SoC. NoC is a higher-level, larger-scale system on a chip, and a network system on a chip. The core idea of ​​NoC technology is to transplant computer network technology into chip design to solve the problem of multi-CPU architecture. Since the nature of the network structure is a multi-CPU system, the network-based architecture is one of the most promising solutions for the multi-CPU system. The on-chip network inherits the concepts of distributed system and computer network. The interconnection structure has parallel communication between various communication modules. The data communication bandwidth is high, the scalability is good, the throughput is large, and it can improve the deep/ultra-deep to a certain extent. Some people claim that NoC will become the mainstream interconnection structure of the next generation of multi-core with the advantages of signal transmission line delay under sub-micron conditions. 1.1 Problems solved by NoC The problems that NoC solves are mainly reflected in the reusability of communication modules and the predictability of communication performance. (1) Increase the reusability of the communication module. In the general SoC concept, reusability is the multiplexing of IP modules. The module-based design method can enhance the reusability of the design, thereby reducing the gap between the manufacturing process and the design capability. The superiority of reusable technology lies in building the entire system with a module-based design, reducing the design time of individual development of each component, and reducing the possibility of human design errors, thus reducing the design and verification time of the system. However, when the manufacturing process develops below 0.13μm, the interconnection delay between modules has become a bottleneck that limits the overall performance of the system. The multiplexing of IP modules alone can no longer meet the overall performance requirements. The on-chip network structure uses communication components. The reusable technology, which connects the routing connections between different resource units through regular communication components, provides solutions for the problems caused by deep sub-micron technology. (2) Strengthen the predictability of communication performance. Due to its regular physical layout and communication network structure, the communication performance of the on-chip network becomes predictable. From the perspective of physical performance, the on-chip network structure determines the predictability of the physical performance of the layout. Except for the clock and power wiring, the interconnection length and bandwidth between the switching units are the same, and the uncertainty and irregularity of the design are limited to the inside of the resource unit, which has no impact on other resource units; from the design From the perspective of verification time, the module-based reusability of the on-chip network makes the design and verification time predictable. Due to the regularity of the on-chip network structure, design issues such as task allocation are divided into resource units, and the overall application is divided into Independent task. In this way, the design of the on-chip network system is largely independent of the specific implementation stage, and the modularization is better, and the predictability of communication performance is increased. 1.2 Advantages of NoC NoC design uses global asynchronous and local synchronization to solve the problems faced by the entire chip's global synchronization. It has good reusability and scalability, and the average communication bandwidth is relatively high. In NoC, the communication between the processing core and the network is completed through a simple handshake protocol, so the electrical parameters and clock signals of the network and each processor can be processed relatively independently, which is easy to control. In addition, asynchronous communication can also be used between the network and the processor, which does not require global synchronization of the system clock, avoiding clock and area problems caused by a huge clock tree, and the large number of local clock lines can greatly reduce system power consumption. The synchronization units of NoC work together under the premise of complying with the communication protocol. If the NoC system needs to be expanded, just add a copy of the existing communication switch in the system, and design a communication interface to integrate the expanded functional units. It can be completed in the NoC network topology. NoC has a reusable and extensible communication mechanism. At the same time, it works in a global asynchronous local synchronization (Glo bal Asynohronized Local Synchronized, GALS) mode. There is no global control signal intervention, so NoC has good scalability. The main indicator to measure NoC performance is communication bandwidth. NoC adopts a global asynchronous and local synchronous communication method. Although it has gained some benefits, it has obvious disadvantages. For example, the real-time communication bandwidth cannot reach the ideal height. However, in terms of the average communication bandwidth of the entire NoC, the global average communication bandwidth is higher than the average communication bandwidth based on the bus method. In short, with the gradual improvement of process integration, NoC is superior to traditional design methods in solving global clock synchronization problems, deep sub-micron effects, scalability, and the gap between design and production. 2 NoC topology The topology is concerned with the layout and interconnection of nodes. The choice of NoC topology has a significant impact on system performance and chip area. NoC can adopt different topological structures according to the needs of the application, which can be divided into regular structure and irregular structure. Compared with the regular topology, the irregular topology can improve performance, reduce power consumption, and reduce area, but at the same time it will cause design problems such as layout design and uneven line length. The topological structure measurement standard is usually based on theoretically affecting the routing cost and performance. In addition to the number of nodes, the number of edges, network dimensions, network diameter, average distance, and bisecting width that are concerned in the ordinary network, The embedded properties of the communication mode should be considered, such as message throughput, transmission delay, power consumption, chip-to-chip, and so on. Multifunction Steam Rice Cooker,Kitchen Rice Cooker,Kitchen Rice Cooker,Automatic Rice Cooker JOYOUNG COMPANY LIMITED , https://www.globaljoyoung.com